Power and fault tolerance are deemed to be two orthogonal optimization objectives in FPGA synthesis, with independent attempts to develop algorithms and CAD tools to optimize each objective. In this paper, we study the relationship between these two optimizations and show that they are, surprisingly, strongly tied to each other. Specifically, we analyze the power and reliability optimization problems in FPGA physical synthesis (i.e., packing, placement, and routing), and show that the intrinsic structures of these two problems are extremely similar. Supported by the post routing results with detailed power and reliability analysis for a wide selection of benchmark circuits, we show that with minimal changes -- fewer than one hundred lines of C code-- an existing power-aware physical synthesis tool kit can be used to minimize the fault rate of a circuit under SEU faults. As a by-product of this study, we also show that one can improve the mean-time-to-failure by 100% with negligible area and delay overhead by performing fault-tolerant physical synthesis for FPGAs. The results from this study show a great potential to develop power and fault-tolerance co-optimized CAD systems.
The benchmark circuits used in the paper can be download here.
Each of these circuits are from IWLS or MCNC benchmark circuit suits
which are mapped to FPGA 4 and 6 input LUTs on an island style FPGA architecture using ABC tool.
The code has been successfully build and ran on Linux 32/64 bit Machines. Please mail for scripts which counts the interconnects and calculate the criticality.
Please download the code here power_fault.tar.gz
1. gunzip power_fault.tar.gz ; tar -xvf power_fault.tar 2. cd power_fault 3. ./install //this script will install the executables. 4. View Readme for further details.
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